Serial communication interfaces are a common element for an integrated circuit processor such as a system on a chip (SoC). An SoC must serve an ever expanding set of functions such as web browsing, email, video gaming, and so on. To interface with its various peripherals during the execution of these functions requires a certain number of pins or terminals. It would be convenient to assign each input/output signal to its own unique pin but increasing the number of pins for an integrated circuit increases its costs. Moreover, even if cost were no issue, an integrated circuit can only fit so many pins onto its surfaces.
To limit the number of required pins, conventional SoCs typically include have one or more serial communication interfaces such as a universal asynchronous receiver transmitter (UART) interface, an inter-integrated circuit (I2C or I3C) interface, or a serial peripheral interface (SPI). A plurality of signals may then be serialized and transmitted through a corresponding serial interface having a single data pin (or pins) that is shared by the various serialized signals.
Although serial interfaces are thus advantageous, the serialization of signals inherently introduces latency. For example, if a one-bit signal has its own unique pin such as for a general purpose input output (GPIO) signal, the resulting one-bit GPIO signal may be transmitted responsive to a single cycle of a system clock. But if the one-bit GPIO signal is serialized with other GPIO signals into a frame such as an 8-bit frame in a virtual GPIO interface, it takes eight clock cycles to transmit the resulting frame (assuming a single data rate with regard to edges of the clock). The serial transmission in a virtual GPIO system would thus take eight times as long to transmit a GPIO signal as compared to a conventional GPIO transmission. The resulting latency may be critical in time-sensitive applications such as for radio front-end control.
Accordingly, there is a need in the art for reducing the latency inherent to serial interfaces.